Data Plane Software Design

Note

What you find here is a draft version of the book, currently consisting of the basic structure, and three full chapters: Introduction, Threading and Statistics.

Contents:

• Introduction
  • Audience
  • Networking Planes
    • Data Plane
    • Control Plane
    • Management Plane
  • Data Plane Applications
    • Low Latency Non Data Plane Applications
    • Low Capacity Data Plane
    • Data Plane Development Kit
    • Data Plane Fast Path
    • Data Plane Slow Path
    • Data Plane Control
    • Reference Architectures
  • Network Function
  • Hardware Platforms
    • Processor
    • Accelerators
    • Memory
  • People
    • Why Data Plane Programming is Easy
    • Why Data Plane Programming is Hard
    • Staffing Data Plane Projects
• Threading
  • Introduction
  • Basic Concepts
    • Threads
    • Process Scheduler
    • Context Switches
  • Standard Threading
    • Overview
    • Language and Language Runtime Impact
    • Life of a Packet
    • System Calls
    • Process Context Switches
    • Latencies
    • Performance Comparison
  • Data Plane Threading
    • Overview
    • EAL Threads
    • Non EAL Threads
    • Control Threads
    • Core Allocation
    • Deployment Example
    • Service Cores
    • Thread Type Summary
    • A Terminology Side Note
    • Real Time Scheduling Policies
• Work Scheduling
  • Introduction
  • Basic Concepts
    • Item of Work
    • Work Scheduler
    • Work Size
    • Flow
    • Work Ordering
  • Work Scheduling Models
    • Run to Completion
  • Pipeline
    • Load balancing
    • Parallism
    • Optimization Points
    • Scheduled Pipeline
    • Static Ingress Load Balancing
  • Dynamic Ingress Load Balancing
• Ethernet Devices
  • Ethernet API
    • Receive and Transmit Queues
  • Hardware NIC Drivers
  • VirtIO Net
  • Memif
  • AF_XDP
• The Packet Buffer
• Protocol Header Processing
  • Header Parsing
  • Byte and Bit Order
  • Data Alignment
  • Aliasing
• Memory Management
  • DPDK Memory Pools
    • Ring versus Stack
    • Per-core Caches
  • DPDK Heap
  • Huge Pages
• Synchronization
  • Staying Safe
    • Thread Safety
    • Asynchronous Signal Safety
    • Preemption Safety
  • Considerations
  • Amdahl’s Law
    • Critical Section Length and Impact
  • C11 Atomics
  • Sequence Locks
  • Spinlocks and Ticketlocks
  • Read-Copy-Update
  • Per Core Data Structures
• Caches
  • Working Set Considerations
    • Staying On Chip
    • DRAM Bandwidth
  • Software Prefetching
    • Cache Line Demotion and Flushing
  • Non Temporal Loads and Stores
• Data Structures
  • Rings
  • Stacks
  • Tables
• Statistics
  • Counters
  • Use Cases
    • Telemetry
  • Requirements
    • Performance
    • Update Propagation Delay
  • Organization
    • Separate versus Integrated Counters
  • Synchronization
    • Shared Non Synchronized Counters
    • Shared Atomic Counters
    • Shared Lock Protected Counters
    • Shared Counters with Per Core Buffering
    • Per Core Counters
    • Performance Comparison
  • Device Statistics
  • Metrics Library
  • Telemetry Library
• Timekeeping
  • System Time Access
  • DPDK Cycles API
    • Measuring Processing Latency
• Timers
  • Timer Wheels
    • DPDK Timer
  • Dispatching Timeouts
    • DPDK Eventdev Timers
• Cryptography
  • On Core Crypto Acceleration
  • Cryptography Devices
• Modularization
  • Module and Interfaces
  • Layering and Dependency Inversion
  • Modular Deployment
• Control Plane
  • Control and Data Plane Division of Concern
    • Layers of Control Planes
  • Control Plane Interface
    • Control Plane Synchronization Strategies
  • Management Plane
• Slow Path
  • Slow and Fast Path Division of Concern
    • Flow Cache Architecture
• Anti Patterns
• Glossary

Indices and tables

• Index

• Search Page